As the internet traffic increases and becomes diverse due to upcoming applications such as the WWW (world wide web), the demand for ATM packet,switches, such as ATM switches, is expected to increase. The current standard for high performance packet switches is ATM. There currently is a lot of hype in the ATM market. However, when the dust settles, customers will clearly see that the current ATM products will be inadequate for several reasons. These products do not truly offer modularity and scalability in terms of performance nor cost. An ideal ATM switch would allow customers to buy a small sized switch initially and increase its size as the need arises without making the previous installation obsolete or making a significant initial investment with an eye toward expansion later. The present invention is a novel packet switch architecture to provide these customers with what they want now: a switch that can grow economically without compromising network performance nor control complexity.
The migration of high bandwidth connections from local area networks to larger networks has increased the size requirements of ATM (Asynchronous Transfer Mode) switches. Current ATM switch products in the market are limited in their scalability, typically due to the high access rates required to a shared buffer memory and the complex interconnections between switching elements.
Existing ATM switch architectures increase their switch size by interconnecting multiple ports by a time-multiplexed bus. Thus the number of ports in these switches are limited by the bandwidth of the backbone bus. Furthermore, the speed of switch controller increases with the size of the switch. In addition to limited scalability, it is typically difficult to grow the switch in a modular fashion. For example, if a customer plans to deploy a 128 ported ATM switch in the future, then it is necessary to purchase the 128 ported switch frame and backbone bus and then purchase additional I/O cards as the need arises. Thus the initial cost to the customer is very high and the size of the final switch size is determined in the initial stage of switch deployment. Current ATM switch products do not offer a clear evolutionary path to large scale switches from current small sized switches. Either customers have to waste initial investment or plan ahead and make major investment in the beginning. Even then they do not offer scalability after one reaches the maximum size of the switch.
There are several advantages of the proposed switch architecture herein. First of all, the proposed switch is truly scalable and modular. A customer can start with as low as a 16 ported switch at the competitive price and grow up to 2048 ported switch without major modification of already invested components. The cost of expanding to a larger switch is linear and the switch does not require a major investment initially. The switch architecture consists of multiple switching modules that are interconnected by a simple and low cost space and time-multiplexed backplane. The major cost of the switch is in the switching modules and the low-cost backplane is reconfigured automatically as the size of the switch grows. The size of the switch can grow simply by adding additional switching modules to existing ones without a priori knowledge of the final size. switching modules are then interconnected via a low-cost programmable backbone, IM (Interconnection Module). The low-cost IM contains no active components and consists of passive elements. IM can be either replaced for the desired switch size at low cost or reprogrammed for additional switching modules if a larger IM was installed initially. Thus the size of the switch can be increased without early decision of what final switch size should be.
Another major advantage of the switch is its robust performance and ability to handle heterogeneous traffic efficiently. The queueing discipline employed in the switch is partially shared buffering. The switch shares a subset of the entire memory space and at the same time it ensures fair access to every user in a heterogenous traffic scenario. Existing shared-memory switches are shown to be biased toward users with heavy traffic load and degrade services to lightly loaded traffic due to memory hogging problems. Thus, a complex control structure is required in existing shared-memory switches to avoid traffic congestion and unfair accesses. Another critical advantage of the switch is its distributed control. The switch has a distributed control and the complexity of control does not grow with the size of the switch. In existing switches, a centralized controller switches packets from input ports to output ports. Furthermore, the speeds of the processor and the memory have to increase in order to accommodate larger number of ports. In the switch architecture of the present invention, each switching module operates independent of the states of other switching modules no matter how many of them are present. Each switch module processes incoming packets using their destination address. Thus, the switching module needs to accommodate packets from its own fixed number of input ports. The speed of the control processor and memory in each switching module does not increase as the size of the switch increases. Distributed control is a major advantage of any scalable architecture due to speed limitation on processors and memory. Furthermore, the cost of implementing a distributed control which requires low speed parts is far lower than a centralized control with high speed components.
The proposed switch architecture consists of multiple switching modules that are interconnected by a simple and low cost space and time-multiplexed backplane. The major cost of the switch is in the switching modules. The low-cost backplane is reconfigured automatically as the size of the switch grows. Each switching module contains an internal buffer that is shared among other switching modules. This switch architecture provides connectivity among different switching modules through a combination of space and time division multiplexing. The intelligent routing of cells through these switching modules allow high throughput and low delay performance comparable to more expensive output queueing switches under random traffic. Under bursty and non-uniform traffic, the switch automatically reconfigures and manages buffers to avoid performance degradation that are inherent in existing switch architectures without complex buffer control mechanisms. Furthermore, multicast traffic can be easily accommodated and is routed efficiently to maximize switch utilization.
Another way to view the switch architecture of the present invention is that it provides scalability through space division switching in conjunction with the time division switching. Switching modules are configured through multiple backbone buses and interconnected in various ways to achieve a desired performance. Switching modules can be interconnected in a symmetric fashion to achieve the minimum hop delay for balanced traffic as discussed below as modulo T design. However, these switching modules can also be configured to take advantage of different traffic requirements. In a client-server traffic scenario, more bandwidth can be allocated among heavily used switching modules thus resulting in an asymmetric configuration. Since the backbone interconnection is programmable, the switch can adapt to different traffic patterns to meet the required performance using the same hardware elements.